T. Moeinfard
Résumé

Analog / Mixed-Signal · Toronto, ON

TaniaMoeinfard

High-Speed Analog Design Engineer

Designing the circuits that move bits cleanly through copper and light — equalisers, latches, clocking and regulators in BiCMOS, CMOS and FinFET, from schematic through layout and tape-out.

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TOP · 1200 × 1000 µm
U5 LDOU6 CLOCK DISTRIBUTIONU7 SAR ADCU1 FFE SUMMERU2 CABLE DRIVERU4 STRONG-ARM LATCHU3 CTLEDIG DIGITAL CONTROL
Fig. 01 — floorplan, illustrative test chip

Along the link

Fig. 02 — blocks she has designed, placed on one serial link. A composite of several projects, not a single product; waveforms are illustrative.
U5 LDOLow-noise, ultra-low-headroom, PSRR below −15 dB · Neuron IPVDD
  1. U1

    FFE summer

    Multi-phase current-integrating summer for a 56 GHz optical transmitter.

    Neuron IP

  2. U2

    Cable driver

    Second-generation BiCMOS driver, reaching up to 3 m of copper.

    Ciena

  3. CH

    Channel

    Loss and reflections smear the bits together.

    Copper · optical

  4. U3

    CTLE

    Continuous-time equaliser optimised for 112 Gbps in FinFET.

    Neuron IP

  5. U4

    Strong-Arm latch

    32 Gbps UCIe slicer; 40% less power after porting to a newer node.

    Neuron IP

U6 Clock distributionRail-to-rail across all corners, <2.5% duty-cycle error with no DCC · Neuron IPCLK

Profile

An analog designer with a strong grip on fundamentals and a proven record of successful tape-outs and testing — at home anywhere between 112 Gbps FinFET equalisers and ultra-low-power ΔΣ converters.

  1. Analog/mixed-signal designer with a strong understanding of analog fundamentals and a proven track record of successful tape-outs and testing.
  2. Expertise in BiCMOS, deep-submicron CMOS and FinFET technologies, including 3nm, 5nm, 12nm, and 22nm nodes.
  3. Proficient with industry-standard EDA tools: Cadence Virtuoso, Synopsys Custom Compiler and HSPICE, Siemens Calibre, Cadence Pegasus, and Quantus.
  4. Experienced in high-speed equalization circuits (CTLE, FFE) and power-management blocks (LDO, bandgap).
  5. Hands-on with EM/IR (Voltus-Fi), automation (Python, Verilog-A), and multi-corner verification methodologies.

Experience

  1. to

    ON, Canada

    Analog Design Engineer at Ciena (acquired Nubis)

    • Driver for Copper CablesDesign, optimization, and layout of the second generation in BiCMOS technology to enable longer reach up to 3 meters for copper cables.

  2. to

    ON, Canada

    Analog Design Engineer at Neuron IP

    • SerDes
      • Low-Power Strong-Arm LatchDesigned for 32Gbps-XSR-NRZ UCIe standard.
      • Porting of Strong-Arm LatchThe optimized design was ported to a more advanced node improving power consumption by 40% while keeping other parameters the same (Clk-to-Q, sensitivity, hysteresis, aperture time, …).
    • LDODesign and verification of several LDOs with various requirements (low-noise, ultra-low headroom, high PSRR (<−15dB using a PMOS pass-device)).
    • FFE for a 56GHz Optical Transmitter
      • Clock DistributionDesign and verification of clock generator and distribution with rail-to-rail signals across all corners and less than 2.5% duty cycle error without a DCC.
      • Current SummerDesign and optimization of multi-phase current integrating summer.
    • Verification Methodology ImprovementCreated a Python-driven framework to automate testbench generation, simulation, and result visualization for analog IPs (LDOs, bandgaps, sense amplifiers) in HSPICE. The tool streamlined netlist integration, pin mapping, and multi-corner analysis, producing performance plots (e.g., PSRR, sensitivity) and tables automatically, achieving an order-of-magnitude reduction in verification effort.
    • High Speed CTLEThis design is optimized for 112 Gbps in FinFET technology.

  3. to

    Toronto, Canada

    Research Assistant at York University

    • Instrumentation Data Converters
      • SAR-Assisted Delta-Sigma ADCDesigned a SAR-assisted ΔΣ ADC using a chopper-stabilized amplifier for ultra-low-power, low-noise neural recording.
      • Second-Order Delta-Sigma ADC with an FIR filterAn ultra-low power design for biomedical application with ENOB of 9.
      • SAR ADC10-bit capacitive SAR ADC designed for neural recording applications.

  4. to

    Toronto, Canada

    Teaching Assistant at York University

    • Several EE and CS courses.

Education

  1. Ph.D., Electrical Engineering

    York University, Toronto, Canada · 2020–2025

    ThesisData Converters for Point of Care Applications

  2. MSc, Electrical Engineering

    York University, Toronto, Canada · 2018–2020

    ThesisAn 8-Channel Bidirectional Neurostimulator IC with a Highly Linear High-Dynamic-Range ADC-Direct Architecture for Simultaneous Recording and Stimulation

  3. BSc, Electrical Engineering

    IUST, Tehran, Iran · 2013–2017

    ThesisDesign and Implementation of a Lock-in Amplifier Used for Atomic Force Microscope

Awards & honours

  • York University Graduate Scholarship
  • York University Entrance Scholarship Award

Publications

  1. 2024

    A Second Order ΔΣ ADC with FIR DAC for DNA Nanopore Readout Interface

    T. Moeinfard, E. Ghafar-Zadeh and S. Magierowski

    IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), 2024 · Kingston, ON, Canada, pp. 632–637

  2. 2022

    A SAR-Assisted DC-Coupled Chopper-Stabilized 20μs-Artifact-Recovery ΔΣ ADC for Simultaneous Neural Recording and Stimulation

    T. Moeinfard, G. Zoidl and H. Kassiri

    IEEE Custom Integrated Circuits Conference (CICC), 2022 · pp. 1–2

  3. 2022

    A 200GΩ-ZIN, <0.2%-THD CT-ΔΣ-Based ADC-Direct Artifact-Tolerant Neural Recording Circuit

    T. Moeinfard and H. Kassiri

    IEEE International Symposium on Circuits and Systems (ISCAS), 2022 · pp. 1901–1905

  4. —

    A Neurostimulator IC with Impedance-Aware Dynamic-Precision One-Shot Charge Balancing

    F. Eshaghi, T. Moeinfard, E. Najafiaghdam and H. Kassiri

    IEEE Solid-State Circuits Letters

  5. 2021

    A Low-power High-gain Inverter Stacking Amplifier with Rail-to-Rail Output

    E. H. T. Shad, T. Moeinfard, M. Molinas and T. Ytterdal

    IEEE International Conference on Design and Test of integrated micro and nano-Systems (DTS), 2021 · pp. 1–6

  6. 2020

    A Power Efficient, High Gain and High Input Impedance Capacitively-coupled Neural Amplifier

    E. H. T. Shad, T. Moeinfard, M. Molinas and T. Ytterdal

    IEEE Nordic Circuits and Systems Conference (NorCAS), 2020 · Oslo, Norway, pp. 1–5

Toolkit

Process technologies

  • BiCMOS
  • Deep-submicron CMOS
  • FinFET
  • 3nm
  • 5nm
  • 12nm
  • 22nm

Circuits

  • CTLE
  • FFE
  • SerDes / Strong-Arm latch
  • Clock generation & distribution
  • LDO
  • Bandgap
  • ΔΣ ADC
  • SAR ADC
  • Cable drivers

Design & layout

  • Cadence Virtuoso — schematic L/XL, ADE/Assembler, layout L/XL
  • Synopsys Custom Compiler
  • Synopsys HSPICE

Verification & signoff

  • Siemens Calibre (LVS/DRC)
  • Cadence Pegasus (physical verification)
  • Quantus (parasitic extraction)
  • Voltus-Fi (EM/IR)
  • Multi-corner verification

Automation

  • Python
  • Verilog-A

The full document

The complete résumé, on one page.

PDF · references available upon request

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